Optimizing The Use of Stream Buffers in Embedded Systems

In here we consider an overall approach to design the memory sub system of embedded systems. We focus on the use of stream buffers versus the use of caches. Stream buffers are useful to handle stream like memory access patterns (mainly array elements in loops) while caches are better suited to handle irregular accesses (e.g. traversing binary trees). Stream buffers are more efficient in terms of power and chip area than caches but may increase the memory bandwidth. In this work we study the tradeoff between these three elements (cache, stream buffers and memory configuration) presenting a system that determines an optimized combination of these three elements. The goal is to maximize the amount of load/store operations that are executed via stream buffers. We use compiler analysis to select and optimize large loops to work with stream buffers and then determine the minimal necessary memory configuration. This include choosing number of DRAM banks and the memory access mode, namely pipeline mode, parallel mode or sequential mode.